1. Field
Example embodiments relate to a semiconductor memory device. Other example embodiments relate to a phase change layer and method of manufacturing the same, and a phase change memory device having the phase change material and methods of manufacturing and operating the phase change memory device.
2. Description of the Related Art
Phase change random access memories (PRAMs) are one type of phase change memory devices, which are next-generation nonvolatile memory devices. The PRAMs may include a storage node comprising a phase change layer. The phase change layer may switch from amorphous to crystalline states and revert back to the amorphous state, or switch from crystalline to amorphous states and revert back to the crystalline state. The phase change layer in a crystalline state may have lower resistance than when in an amorphous state. PRAMs may record data based on the principle that the resistance of the phase change layer varies depending on the phase of the phase change layer.
A first temperature (melting point) at which the phase change layer changes from crystalline to amorphous states may be higher than a second temperature (crystallization point) at which the phase change layer changes from amorphous to crystalline states. As electric current flows through the phase change layer during operation of a PRAM, Joule heat may be generated, which causes heating of the phase change layer to the first temperature or the second temperature. When the first temperature is reached by causing a first current to flow through the phase change layer during a PRAM operation, the first current may be referred to as a ‘reset current’. When the second temperature is reached by causing a second current to flow through the phase change layer, the second current may be referred to as a ‘set current’. Current may flow into the phase change layer through a switching device during the PRAM operation to generate Joule heat, and thus, the magnitude of current flowing into the phase change layer during the PRAM operation may not be greater than that of current that the switching device may support.
Like in other memory devices, increasing integration density may be important in PRAM development. One method of increasing integration density of a PRAM is to reduce the size of the switching device. However, as the size of the switching device, e.g., a transistor, is reduced, the magnitude of current that the switching device may support decreases, which means that a maximum current that may flow through the phase change layer decreases. Thus, the reset current flowing through the phase change layer may be low enough to increase the integration density of the PRAM.
A Ge2Sb2Te5 (GST) layer may be used as the phase change layer. The GST layer may have a relatively high melting point of about 620° C. and a relatively high reset current may be required to increase the temperature of the GST layer to about 620° C. Thus, when the size of the switching device is reduced in a current of the PRAM using the GST layer as the phase change layer (hereinafter called a ‘conventional PRAM’), the switching device may not permit the reset current required to increase the temperature of the GST layer to about 620° C. For example, the conventional PRAM may not actually achieve increased integration density without replacing the GST layer.
Another drawback of the conventional PRAM is that cell disturbance may occur between two adjacent cells because the GST layer in the conventional PRAM has a relatively high melting point of about 620° C., however, a relatively low crystallization point of about 160° C. The cell disturbance may refer to a phenomenon by which a cell, which is adjacent to a selected cell that is being accessed, is disturbed. The conventional PRAM may also exhibit undesirable data retention and/or IR reflow characteristics.